1. Field of the Invention
The present invention is directed to an asynchronous edge triggered RS flip-flop circuit for use in creating asynchronous digital circuits of the so-called "self-clocking" and "self-timing" type.
2. Brief Discussion of the Art
In order to better understand the flip-flop circuit that is the subject of the present invention, reference is first made to FIGS. 1 to 5 representing a conventional RS flip-flop, commonly employed as an "elementary" circuit, which is used to form sequential digital networks. It is commonly constructed in a solid state form, i.e., as an "integrated circuit", and when duly associated with other circuits permits great flexibility in design application.
A conventional RS flip-flop circuit requires a particular control command for switching, as explained below and has at least one output Q and two inputs: S (set) and R (reset), respectively, for "setting" and "resetting" the output state of the device.
FIG. 1 shows the block diagram of a conventional RS flip-flop 8. The RS flip-flop 8 is said to be "set" when output Q assumes the "true" value (Q=1, in positive logic). The output symbol will be represented with Q(1), thus also denoting the symbol of the operation logic type (1, according to positive logic). Conversely, the RS flip-flop 8 is said to be "reset" when the same Q output assumes the "false" value (Q=0, in positive logic). Conventional RS flip-flops also have another possible output Q' (0), representing, except for a slight time difference, the complement (negative logic) of output Q.
A significant transition in signal level applied to the active input S (set) (0.fwdarw.1, in positive logic) will set the device, whereas a corresponding significant transition at the input R (reset) (0 .fwdarw.1, in positive logic) will reset it.
In the ensuing description the input symbols will be expressed with S(1) and R(1), i.e., assigning to the letters the logical level achieved after the significant transition. Consequently the Set input is enabled and the Reset input is disabled when the flip-flop is reset Q(1) =0, while the Reset input is enabled and the Set input is disabled when the flip-flop is set Q(1)=1. The significant transition which has to be applied to the active set and reset inputs in order to change the device state will be represented in both cases by the variation (0.fwdarw.1) of that input.
The input signal transitions (1.fwdarw.0) applied to the set and reset inputs will have no effect on the state assumed by the flip-flop. Obviously it is impossible to set a flip-flop that has already been set as well as to reset an already reset one. In addition, the correct performance of the set and reset control commands will occur only on condition that the significant transition applied to the input currently enabled (e.g., set) occurs when the other input (e.g., reset) is disabled.
FIG. 2 shows the timing diagram of the conventional RS flip-flop 8 operation, while FIG. 3 shows a typical RS flip-flop logical circuit employing a pair of cross-coupled NOR gates 9 and 10. As will be described below, cross-coupled NAND gates can also be used to form an RS flip-flop.
The FIG. 2 timing diagram shows that when the set input (S(1)) goes high (positive), it causes the Q' signal to go low (negative). When this happens, and the reset input (R(1)) remains low, (that is, disabled) the Q(1) output signal goes high (positive) placing the flip-flop 8 in a set condition. FIG. 2 also shows that when the reset input (R(1)) goes high (positive), it causes the Q(1) output to go low (negative). When this occurs and the set input remains low (that is, disabled), the Q' signal goes high (positive) placing flip-flop 8 in a reset state.
For completeness sake and in order to better clarify the comparisons that are about to be made, the logical equation of the RS flip-flop 8 is given hereunder: EQU Q=R (S V Q),
where " " represents the logical AND operator and "V" the logical OR operator. FIG. 4 is a Boolean operation table illustrating transitions and states of the RS flip-flop 8. Whenever the procedure of enabling one input while disabling the other is disregarded, i.e., active input signal transitions (e.g., 0 .fwdarw.1) are applied to both inputs, the result is an anomalous behavior (see FIG. 4, notes 4.1 and 4.2). The flip-flop 8 assumes the state (Q =0, Q'=0), and consequently it is neither set nor reset, as shown by the timing diagram in FIG. 5. In this case the offset mode of the set and reset commands will determine the next state of the flip-flop (see FIG. 4, notes 5.1 and 5.2).
In addition whenever, starting with the "non-set" and "non-reset" condition (Q=0, Q'=0), one applies at the same time to both set and reset inputs the transition (1.fwdarw.0), this will result in a lack of determination of state assumed by the flip-flop (see FIG. 4, note 6).
As a conclusion, it can be observed that the ordinary RS flip-flop responds to the significant transitions applied to the set and reset inputs (0.fwdarw.1, in positive logic), but the state assumed will still depend on the signals applied to the set and reset inputs even after the time which is needed for the new state realization to occur has elapsed. Hence it is necessary that one input must be disabled before applying a significant transition to the other. Following a similar analysis to the above, the same problem exists for an RS flip-flop operating with negative logic both for inputs and outputs.